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1 of 20 011107 features ? holds microprocessor in check during power transients ? halts and restarts an out-of-control microprocessor ? monitors pushbutton for external override ? warns microprocessor of an impending power failure ? converts cmos sram into nonvolatile memory ? unconditionally write protects memory when power supply is out of tolerance ? consumes less than 100 na of battery current at 25c ? controls external power switch for high current applications ? accurate 10% power supply monitoring ? optional 5% power supply monitoring designated ds1236a-5 ? provides orderly shutdown in nonvolatile microprocessor applications ? supplies necessary control for low-power stop mode in battery operated hand-held applications ? standard 16-pin dip or space-saving 16-pin soic ? optional industrial temperature range -40c to +85c pin assignment pin description v bat - +3-volt battery input v cco - switched sram supply output v cc - +5-volt power supply input gnd - ground pf - power-fail (active high) pf - power-fail (active low) wc/ sc - wake-up control (sleep) rc - reset control in - early warning input nmi - non-maskable interrupt st - strobe input ceo - chip enable output cei - chip enable input pbrst - pushbutton reset input rst - reset output (active low) rst - reset output (active high) description the ds1236a micromanager chip provides all the necessary functions for power supply monitoring, reset control, and memory backup in microprocessor-based systems. a pr ecise internal voltage reference and comparator circuit monitor po wer supply status. when an out-o f-tolerance condition occurs, the microprocessor reset and power-fail outputs are for ced active, and static ram control unconditionally write protects external memory. the ds1236a also provides early warn ing detection of a user-defined threshold by driving a non-maskable interrupt. exte rnal reset control is pr ovided by a pushbutton reset ds1236a micromanager chip www.maxim-ic.com 16-pin soic (300-mil) see mech. drawings section vbat vcco vcc rst rst pbrst 1 2 3 1 6 1514 gnd cei 4 1 3 pf pf wc/sc ceo st nmi 5 6 7 1211 1 0 rc in 8 9 16-pin dip (300-mil) see mech. drawings section vbat vcco vcc rst rst pbrst 1 2 3 16 15 14 gnd cei 4 13 pf pf wc/sc ceo st nmi 5 6 7 12 11 10 rc in 8 9 downloaded from: http:///
ds1236a 2 of 20 input which is debounced and activates reset outputs. an internal watch dog timer can also force the reset outputs to the active state if the st robe input is not driven low prio r to watchdog timeout. reset control and wake-up/sleep control inputs also provide the n ecessary signals for orderly shutdown and start-up in battery backup and battery operated applications. a block diagram of the ds1236a is shown in no tag. pin description pin name description v bat +3v battery input provides nonvolat ile operation of control functions. v cco v cc output for nonvolatile sram applications. v cc +5v primary power input. pf power-fail indicator, active high, used for external power switching as shown in no tag. pf power-fail indicator, active low. wc/ sc wake-up and sleep control. invokes low-power mode. rc reset control input. determin es reset output . normally lo w for nmos processors and high for battery backed cmos processors. in early warning power-fail i nput. this voltage sense point can be tied (via resistor divider) to a user-selected voltage. nmi non-maskable interrupt. used in conjunction with the in pin to indicate an impending power failure. st strobe input. a high-to-low transition w ill reset the watchdog timer, indicating that software is still in control. ceo chip enable output. used with nonvolatile sram applications. cei chip enable input. pbrst pushbutton reset input. rst active low reset output. rst active high reset output. processor mode a distinction is often made betw een cmos and nmos processor systems. in a cmos system, power consumption may be a concern, and nonvolatile operati on is possible by battery backing both the sram and the cmos processor. all resources w ould be maintained in the absence of v cc . a power-down reset is not issued since the low-power m ode of most cmos processors (stop) is terminated with a reset. a pulsed interrupt ( nmi ) is issued to allow the cmos processor to invoke a sleep mode to save power. for this case, a power-on reset is desi rable to wake up and initialize the processor. the cmos mode is invoked by connecting rc to v cco . an nmos processor consumes more power, and consequently may not be battery backed. in this case, it is desirable to notify the proce ssor of a power-fail, then keep it in reset duri ng the loss of v cc . this avoids intermittent or aberrant operation. on power-up, the processor will continue to be reset until v cc reaches an operational level to provide an orderly start. the nmos mode is invoked by connecting rc to ground. downloaded from: http:///
ds1236a 3 of 20 power monitor the ds1236a employs a band gap voltage reference a nd a precision comparator to monitor the 5-volt supply (v cc ) in microprocessor-based systems. when an out-of-tolerance conditi on occurs, the rst and rst outputs are driven to the active state. the v cc trip point (v cctp ) is set for 10% operation so that the rst and rst outputs will become active as v cc falls below 4.5 volts (4.37 typical). the v cctp for the 5% operation option (ds1236a-5) is set for 4.75 volts (4.62 typical). the rst and rst signals are excellent for microprocessor reset c ontrol, as processing is stopped at the last possible moment of in- tolerance v cc . on power-up, the rst and rst signals are held active for a minimum of 25 ms (100 ms typical) after v cctp is reached to allow the power supply a nd microprocessor to stabilize. note: the operation described above is obtaine d with the reset control pin (rc) connected to gnd (nmos mode). please review the reset control section for more information. watchdog timer the ds1236a provides a watchdog timer function which forces the rst and rst signals to the active state when the strobe input ( st ) is not stimulated for a predetermined time period. this time period is 400 ms typically with a maximum timeout of 600 ms. the watchdog timeout period begins as soon as rst and rst are inactive. if a high-to-low transition occurs at the st input prior to timeout, the watchdog timer is reset and begins to time out again. the st input timing is shown in no tag. to guarantee the watchdog timer does not time out, a high-to-low transition on st must occur at or less than 100 ms (minimum timeout) from a reset. if the watchdo g timer is allowed to time out, the rst and rst outputs are driven to the active state for 25 ms minimum. the st input can be derive d from microprocessor address, data, and/or control signals. under norma l operating conditions, these signals would routinely reset the watchdog timer prior to timeout. if the wa tchdog timer is not required, two methods have been provided to disable it. permanently grounding the in pin in the cmos m ode (rc=1) will disable the watchdog. in normal operation with rc=1, the watchdog is disabl ed as soon as the in pin is below v tp . with in grounded, an nmi output will occur only at power-up, or when the st pin is strobed. as shown in the no tag, a falling edge on st will generate an nmi when in is below v tp . this allows the processor to verify that power is between v tp and v cctp , as an nmi will be returned immediately after the st strobe. the watchdog timer is not affected by the in pin when in nmos mode (rc=0). if the nmi signal is required to monitor supply voltages, the watchdog may also be disabled by leaving the st input open. independent of the state of the rc pin, the watchdog is also disabled as soon as v cc falls to v cctp . pushbutton reset an input pin is provided on the ds1236a for direct connection to a pushbutton. the pushbutton reset input requires an active low signal. internally, this input is pulled high by a 10k resistor whenever v cc is greater than v bat . the pbrst pin is also debounced and timed such that the rst and rst outputs are driven to the active state for 25 ms minimum. this 25 ms delay begins as the pushbutton is released from a low level. a typical example of the power mon itor, watchdog timer, and pushbutton reset connections are shown in no tag. the pbrst input is disabled whenever the in pin voltage level is less than v tp and the reset control (rc) is tied high (cmos mode). the pbrst input is also disabled whenever v cc is below v bat . timing of the pbrst -generated rst is illustrated in figure 1. downloaded from: http:///
ds1236a 4 of 20 non-maskable interrupt the ds1236a generates a non-maskable interrupt nmi for early warning of power failure to a microprocessor. a precision comparator monitors the vol tage level at the in pin relative to a reference generated by the internal band gap. the in pin is a high-impedance input allowing for a user-defined sense point. an external resistor vo ltage divider network (no tag) is us ed to interface with high voltage signals. this sense point may be derived from the re gulated 5-volt supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 2.54 volts, the proper values for r1 and r2 can be determined by the equati on as shown in no tag. proper operation of the ds1236a requires that the voltage at the in pin be limited to v in . therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in no tag. a simple approach to solving this equation is to select a value for r2 high e nough to keep power consumption low, and solve for r1. the flexibility of the in input pin al lows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for micropro cessor shutdown between nmi and rst or rst . when the supply being monitored decays to th e voltage sense point, the ds1236a pulses the nmi output to the active state for a minimum of 200 s. the nmi power-fail detection circui try also has built-in time domain hysteresis. that is, the monitored supply is sampled periodically at a rate determined by an internal ring oscillator runni ng at approximately 30 khz (33 s/cycle). three consecutive samplings of out-of-tolerance supply (below v sense ) must occur at the in pin to activate nmi . therefore, the supply must be below the voltage sense point for approximately 100 s or the comparator will reset. in this way, power supply noise is removed from the monitoring function, preventin g false trips. during a power-up, any detected in pin levels be low v tp by the comparator are disabled from reaching the nmi pin until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . removal of an active low level on the nmi pin is controlled by either an internal timeout (when in pin is less than v tp ) or by the subsequent rise of the in pin above v tp . the initiation and removal of the nmi signal during power-up results in an nmi pulse of from 0 s minimum to 500 s maximum, depending on the relative voltage relationship between v cc and the in pin voltage. as an example, when the in pin is tied to ground during power-up, the intern al timeout will result in a pulse of 200 s minimum to 500 s maximum. in contrast, if the in pin is tied to v cco during power-up, nmi will not produce a pulse on power-up. note that a fast-slewi ng power supply may cause the nmi to be virtually nonexistent on power-up. this is of no consequence, however, since an rst will be active. downloaded from: http:///
ds1236a 5 of 20 ds1236a functional block diagram figure 1 downloaded from: http:///
ds1236a 6 of 20 if the in pin is connected to v cco , the nmi output will pulse low as v cc decays to v cctp in the nmos mode (rc=0). in the cmos mode (rc=v cco ) the power-down of v cc out of tolerance at v cctp will not produce a pulse on the nmi pin. given that any nmi pulse has been completed by the time v cc decays to v cctp , the nmi pin will remain high. the nmi voltage will follow v cc down until v cc decays to v bat . once v cc decays to v bat , the nmi pin will either remain at v ohl or enter tri-state mode as determined by the rc pin (see reset control section). memory backup the ds1236a provides all of the necessa ry functions required to batter y back a static ram. first, a switch is provided to dir ect sram power from th e incoming 5-volt supply (v cc ) or from an external battery (v bat ), whichever is greater. this switched supply (v cco ) can also be used to battery back a cmos microprocessor. for more information about nonvol atile processor applicati ons, review the reset control and wake control sections. second, th e same power-fail detecti on described in the power monitor section is used to hol d the chip enable output ( ceo ) to within 0.3 volts of v cc or to within 0.7 volts of v bat . this write protection mechanism occurs as v cc falls below v cctp as specified. if cei is low at the time power-fail detection occurs, ceo is held in its present state until cei is returned high or the period t ce expires. this delay of write protection until the current memory cycle is completed prevents the corruption of data. if ceo is in an inactive state at the time of v cc -fail detection, ceo will be unconditionally disabled within t cf . during nominal supply conditions ceo will follow cei with a maximum propagation delay of 20 ns. no tag show s a typical nonvolatile sram application. the ds1236a unlike the ds1236 can be operated without a battery. in this method of operation the v bat , pin 1, must be grounded. in general, it would also be expected to have the rc, pin 8, grounded (nmos mode) since no battery backup is available. freshness seal in order to conserve battery capacity during initial construction of an end system, the ds1236a provides a freshness seal that electrically disconnects the battery. this m eans that upon battery attach, the v cco output will remain inactive until v cc is applied. this prevents v cco from powering other devices when the battery is first attached, and v cc is not present. once v cc is applied, the freshness seal is broken and cannot be invoked again without subsequent removal and reattachment of the battery. power switching when larger operating currents are required in a ba ttery backed system, the 5-volt supply and battery supply switches internal to the ds1236a may not be large enough to support the required load through v cco with a reasonable vo ltage drop. for these a pplications, the pf and pf outputs are provided to gate external power switching devices. as shown in figure 8, power to the load is switched from v cc to battery on power-down, and from battery to v cc on power-up. the ds1336 is designed to use the pf output to switch between v bat and v cc it provides better leakage and switchover performance than currently available discrete components. the transition threshold for pf and pf is set to the external battery voltage v bat , allowing a smooth transition between sources . the load applied to the pf pin from the external switch will be supplied by the battery. therefore, if a discre te switch is used, this load should be taken into consideration when sizing the battery. reset control as mentioned above, the ds1236a supports two modes of operation. the cmos mode is used when the system incorporates a cmos microprocessor which is battery backed. the nmos mode is used when a non-battery backed processor is inco rporated. the mode is selected by the rc (reset control) pin. the level of this pin distinguishes timing and level control on rst, rst , and nmi outputs for volatile processor operation versus nonvola tile battery backup or battery-ope rated processor applications. downloaded from: http:///
ds1236a 7 of 20 st/input timing figure 2 nmi/from st/input figure 3 downloaded from: http:///
ds1236a 8 of 20 power monitor, watchdog figure 4 pushbutton reset timing figure 5 downloaded from: http:///
ds1236a 9 of 20 non-maskable interrupt figure 6 example 1: 5-volt supply, r2 = 10k ohm, v sense = 4.80 volts 4.80 = 10 k 10 k r1 + x 2.54 r1 = 8.9k ohm example 2: 12-volt supply, r2 = 10k ohm, v sense = 9.00 volts 9.00 = 10 k 10 k r1 + x 2.54 r1 = 25.4k ohm v max = 2.54 9.00 x 5.00 = 17.7 volts nonvolatile sram figure 7 downloaded from: http:///
ds1236a 10 of 20 when the rc pin is tied to ground, the ds1236a is de signed to interface with nmos processors which do not have the microamp currents required during a battery backed mode. grounding the rc pin does, however, continue to support non volatile backup of system sram memory. nonvolatile systems incorporating nmos processors generally require that only the sram memory and/or timekeeping functions be battery backed. when the processor is not battery backed (rc = 0), all si gnals connected from the processor to the ds1236a are disconnected from the backup battery supply, or grounded when system v cc decays below v bat . in the nmos processor system, th e principal emphasis is placed on giving early warnings with nmi , then providing a con tinuously active rst and rst signal during power-down while isolating the backup batte ry from the processor during a loss of v cc . during power-down, nmi will pulse low for a minimum of 200 s, and then return high. if rc is tied low (nmos mode), the voltage on nmi will follow v cc until v cc supply decays to v bat , at which point nmi will enter tri-state (see timing diagram). also, upon v cc out of tolerance at v cctp , the rst and rst outputs are driven active and rst will follow v cc as the supply decays. on power-up, rst follows v cc up, rst is held low, and both remain active for t rst after valid v cc . during a power-up from a v cc voltage below v bat , any detected in pin levels below v tp are disabled from reaching the nmi pin until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . removal of an active low level on the nmi pin is controlled by either an internal timeout (when the in pin is less than v tp ), or by the subsequent ri se of the in pin above v tp . the initiation a nd removal of the nmi signal results in an nmi pulse of 0 s minimum to 500 s maximum during power-up, depending on the relative voltage relationship between v cc and the in pin. as an example, when the in pin is tied to ground, the internal timeout wi ll result in a pulse of 200 s minimum to 500 s maximum. in contrast, if the in pin is tied to v cco , nmi will not produce a pulse on power-up. connecting the rc pin to a high (v cco ) invokes cmos mode and provid es nonvolatile s upport to both the system sram as well as a low power cmos pro cessor. when using cmos microprocessors, it is possible to place the microprocessor into a very low-pow er mode termed the stop or halt mode. in this state the cmos processor requires only microa mp currents and is fully capable of being battery backed. this mode generally allows the cmos micropr ocessor to maintain the contents of internal ram as well as state control of i/o ports during battery backup. the processor can subsequently be restarted by any of several different signals. to maintain this low-power state, the ds1236a issues no nmi and/or reset signals to the proce ssor until it is time to bring the processor back into fu ll operation. to support the low-power processor battery backed mode (rc = 1), the ds1236a provides a pulsed nmi for early power failure warning. waiting to in itiate a stop mode until after the nmi pin has returned high will guarantee the processor that no other active nmi or rst/ rst will be issued by the ds1236a until one of two conditions occurs: 1) voltage on the pin rises above v tp , which activates the watchdog, or 2) v cc cycles below then above v bat , which also results in an active rst and rst . if v cc does not fall below v cctp , the processor will be restarte d by the reset derived from the wa tchdog timer as the in pin rises above v tp . with the rc pin tied to v cco , rst and rst are not forced active as v cc collapses to v cctp . the rst is held at a high level via the external battery as v cc falls below battery potential. this mode of operation is intended for applications in which the processor is ma de nonvolatile with an external source, and allows the processor to power down into a stop mode as signaled from nmi at an earlier voltage level. the nmi output pin will pulse low for t nmi following a low voltage dete ct at the in pin of v tp . following t nmi , however, nmi will also be held at a high level (v bat ) by the battery as v cc decays below v bat . on power-up, rst and rst are held inactive until v cc reaches v bat , then rst and rst are driven active for t rst . if the in pin falls below v tp during an active reset, the reset outputs will be forced inactive by downloaded from: http:///
ds1236a 11 of 20 the nmi output. in addition, as long as the in pin is less than v tp , stimulation of the st pin will result in additional nmi pulses. in this way, the st pin can be used to allow the cmos processor to determine if the supply voltage, as monitored by the in pin, is a bove or below a selected operating value. this is illustrated in no tag. as discusse d above, the rc pin determines the timing relationships and levels of several signals. the following section describes th e power-up and power-down timing diagrams in more detail. timing diagrams this section provides a description of the timing diagrams shown in figure 9, figure 10, figure 11, and figure 12. these diagrams show the relative timing an d levels in both the nmos and the cmos mode for power-up and down. figure 9 illustrates the re lationship for power-down in cmos mode. as v cc falls, the in pin voltage drops below v tp . as a result, the processor is notified of an impending power failure via an active nmi , which allows it to enter a sleep m ode. as the power falls further, v cc crosses v cctp , the power monitor trip point. since the ds1236a is in cmos mode, no reset is generated. the rst voltage will follow v cc down, but will fall no further than v bat . at this time, ceo is brought high to write protect the ram. when the v cc reaches v bat , a power-fail is issu ed via the pf and pf pins. figure 10 illustrates operation of the power-down sequence in nmos mode. once again, as power falls, an nmi is issued. this gives the processor time to sa ve critical data in nonvolatile sram. when v cc reaches v cctp , an active rst and rst are given. the rst voltage will follow v cc as it falls. ceo , pf, and pf will operate in a similar manner to cmos mode. notice that the nmi will tri-state to prevent a loss of battery power. figure 11 shows the power-up sequence for the nmos mode. as v cc slews above v bat , the pf and pf pins are deactivated. an active reset occurs as well as an nmi . although the nmi may be short due to slew rates, reset will be maintained for the standard t rst timeout period. at a later time, if the in pin falls below v tp , a new nmi will occur. if the processor does not issue a st , a watchdog reset will also occur. the second nmi and rst are provided to illu strate these possibilities. figure 12 illustrates the power-up timing for cmos mode. the principal difference is that the ds1236a issues a reset immediately in the nmos mode. in cm os mode, a reset is issu ed when in rises above v tp . depending on the processor type, the nmi may terminate the stop mode in the processor. wake control/sleep control the wake/sleep control input (wc/ sc ) allows the processor to disabl e all comparators on the ds1236a before entering the stop mode. this feature allows the ds1236a, processo r, and static ram to maintain nonvolatility in the lowest power mode possible. the processor ma y invoke the sleep mode in battery- operated applications to conserve battery capacity when an absence of activity is detected. the operation of this signal is shown in figure 13. the ds1236a may subsequently be re started by a high-to-low transition on the pbrst input through human interface via a keybo ard, touchpad, etc. the processor will then be restarted as the watc hdog times out and drives rst and rst active. the ds1236a can also be started up by forcing the wc/ sc pin high from an external source. also, if the ds1236a is placed in a sleep mode by the processor and system power is lost, the ds1236a will wake up the next time v cc rises above v bat . these possibilities are illustrated in figure 14. when the sleep mode is invoked during normal power-valid conditions, all operation on the ds1236a is disabled, thus leaving the nmi , rst, and rst outputs disabled as well as the st and in inputs. however, a loss of power during a sleep mode will result in an active rst and rst when the rc pin is downloaded from: http:///
ds1236a 12 of 20 grounded (nmos mode). if the rc pin is tied high, the rst and rst pins will remain inactive during power-down in a sleep mode. rem oval of the sleep mode by the pbrst input is not affected by the in pin threshold at v tp when the rc pin is tied high (cmos mode). subsequent power-up of the v cc supply with the rc pin tied high will activate the rst and rst outputs as the main supply rises above v bat . a high-to-low transition on the wc/ sc pin must follow a high-to-low transition on the st pin by t wc to invoke a sleep mode for the ds1236a. power switching figure 8 downloaded from: http:///
ds1236a 13 of 20 cmos mode power-down (rc = v cco ) figure 9 downloaded from: http:///
ds1236a 14 of 20 nmos mode power-down (rc = gnd) figure 10 downloaded from: http:///
ds1236a 15 of 20 nmos mode power-up (rc = gnd) figure 11 downloaded from: http:///
ds1236a 16 of 20 cmos mode power-up (rc = v cco ) figure 12 downloaded from: http:///
ds1236a 17 of 20 wake/sleep control figure 13 options for invoking wakeup figure 14 downloaded from: http:///
ds1236a 18 of 20 absolute maxi mum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground -0.5v to v cc + 0.5v operating temperature 0c to 70c operating temperature (industrial ve rsion) -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the opera tion sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. recommended dc operating condit ions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 supply voltage (5% option) v cc 4.75 5.0 5.5 v 1 input high level v ih 2.0 v cc +0.3 v 1 input low level v il -0.3 +0.8 v 1 in input pin v in -0.3 v cc +0.3 v 1 battery input v bat 0 4.0 v 1 dc electrical characteristics (0 c to 70 c; v cc = 4.5v to 5.5v) parameter symbol min typ max units notes supply current i cc 4 ma 2 sleep supply current in sleep mode i cc 20 a battery current i bat 0.1 a 2 supply output current (v cco =v cc - 0.3v) i cc01 100 ma 3 supply output current in data retention (v cc < v bat ) i cc02 1 ma 4 supply output voltage v cco v cc -0.3 v 1 battery backup voltage v cco v bat -0.7 v 1, 6 low level @ rst v ol 0.4 v 1 output voltage @ -500 a v oh v cc -0.5v v cc -0.1v v 1 ceo and pf output v ohl v bat -0.7 v 1, 6, 19 pbrst pull-up resistor r pbrst 10k input leakage current i li -1.0 +1.0 a 18 output leakage i lo -1.0 +1.0 a 18 output current @ 0.4v i ol 4.0 ma 12 output current @ 2.4v i oh -1.0 ma 13 downloaded from: http:///
ds1236a 19 of 20 parameter symbol min typ max units notes power sup. trip point v cctp 4.25 4.37 4.50 v 1 power supply trip (5% option) v cctp 4.50 4.62 4.75 v 1 in input pin current i ccin -1.0 +1.0 a in input trip point v tp 2.5 2.54 2.6 v 1 ac electrical characteristics (0 c to 70 c; v cc = 4.5v to 5.5v) parameter symbol min typ max units notes v cc fail detect to rst, rst t rpd 40 100 175 s v tp to nmi t ipd 40 100 175 s reset active time t rst 25 100 150 ms nmi pulse width t nmi 200 300 500 s 14 st pulse width t st 20 ns 20 pbrst @ v il t pb 40 ms v cc slew rate 4.75 to 4.25 t f 300 s chip enable propagation delay t pd 20 ns v cc fail to chip enable high t cf 7 12 44 s 17 v cc valid to rst, rst (rc=1) t fpu 100 ns v cc valid to rst & rst t rpu 25 100 150 ms 5 v cc slew to 4.24 to v bat t fb1 10 s 7 v cc slew 4.25 to 4.75 v bat t fb2 100 s 8 chip enable output recovery time t rec .1 s 9 v cc slew 4.25 to 4.75 t r 0 s chip enable pulse width t ce 5 s 10 watchdog time delay t td 100 400 600 ms st to wc/ sc t wc 0.1 50 s v bat detect to pf, pf t ppf 2 s 7 st to nmi t stn 30 ns 11 nmi to rst & rst t nrt 30 ns v bat detect to rst & rst t arst 200 s 15 v cc valid to rst, rst t brst 30 100 150 s 16 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf downloaded from: http:///
ds1236a 20 of 20 notes: 1. all voltages referenced to ground. a 0.1 f capacitor is recommended between v cc and gnd. 2. measured with v cco , ceo , pf, pf , st , pbrst , rst, rst , and nmi pin open. i bat specified at 25 c. 3. i cco1 is the maximum average load which the ds1236a can supply at v cc -0.3v through the v cco pin during normal 5-volt operation. 4. i cco2 is the maximum average load whic h the ds1236a can supply through the v cco pin during data retention battery supply operation, with a maximum drop of 0.8 volts. 5. with t r = 5 s. 6. v cco is approximately v bat -0.5v at 1 a load. 7. sleep mode is not invoked. 8. sleep mode is invoked. 9. t rec is the minimum time required before cei / ceo memory access is allowed. 10. t ce maximum must be met to ensure data integrity on power loss. 11. in input is less than v tp but v cc greater than v cctp . 12. all outputs except rst which is 25 a minimum. 13. all outputs except rst and nmi , which is 25 a maximum. 14. pulse width of nmi requires that the in pin remain below v tp . if the in pin returns to a level above v tp for a period longer than t ipd and before the t nmi period has elapsed, the nmi pin will immediately return to a high. 15. in pin greater than v tp when v cc supply rises to v bat . example: in tied to gnd. 16. in pin less than v tp when v cc supply rises to v bat . 17. cei low. 18. the wc/ sc pin contains an internal latch which drives back on to the pin. this latch requires +200 amps to switch states. the st pin will sink 50 amps in normal operation and 1 amp in the sleep mode. 19. if no battery is attached (i.e., v bat =gnd) then v ohl will track v cc . 20. st should be active low before the wa tchdog is disabled (i.e., before the st input is tristated). downloaded from: http:///

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